-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;
  USE work.faw_types.ALL;
  
  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS 

  -- Component Declaration
          COMPONENT ShiftRegister_SIPO_test
          PORT(
                  data_in : in  STD_LOGIC_VECTOR (7 downto 0);
						clk : inout  STD_LOGIC;
						en : inout  STD_LOGIC_VECTOR (SR_CELLS-1 downto 0);
						sset : in  STD_LOGIC;
						sclear : in  STD_LOGIC;
						data_out : out  SR_DATA_OUT_BUS;
			  internal_bus: inout SR_DATA_OUT_BUS
                  );
          END COMPONENT;
          

			signal data_in :   STD_LOGIC_VECTOR (7 downto 0);
			signal clk :   STD_LOGIC;
			signal en :   STD_LOGIC_VECTOR (SR_CELLS-1 downto 0);
			signal sset :   STD_LOGIC;
			signal sclear :   STD_LOGIC;
			signal data_out : SR_DATA_OUT_BUS;
			signal  internal_bus: SR_DATA_OUT_BUS;
			
			constant clock_period : time := 10 ms;
 BEGIN
  -- Component Instantiation
          uut: ShiftRegister_SIPO_test PORT MAP(
                  data_in => data_in,
                  clk => clk,
						en => en,
						sset => sset,
						sclear => sclear,
						data_out => data_out,
						internal_bus=>internal_bus
          );


		clock_process :process
		begin
			clk <= '0';
			clk<='0';
			wait for clock_period/2;
			clk <= '1';
			clk<='1';
			wait for clock_period/2;
		end process;
  --  Test Bench Statements
  
     tb : PROCESS
     BEGIN

		sset<='1';
		sclear<='0';
		en<="11101";
		wait for clock_period; 
			
		sset<='0'; 
		wait for clock_period;
		
		for i in 0 to SR_CELLS-1 loop
			data_in<=std_logic_vector(to_unsigned( i ,8));
			en<="01111";
			wait for clock_period;	
		end loop;
		
		wait for 2*clock_period;
		
		for i in 0 to SR_CELLS-1 loop
			data_in<=std_logic_vector(to_unsigned( 5*i+1 ,8));
			en<="11111";
			wait for clock_period;	
		end loop;
		
		
       
     END PROCESS tb;
  --  End Test Bench 

  END;
